Nvidia’s Blackwell chip design pairs two large graphics processing unit dies with eight HBM3E memory stacks, a combination that requires Taiwan Semiconductor Manufacturing Company’s CoWoS packaging at scale. CoWoS, or Chip on Wafer on Substrate, brings logic dies and high-bandwidth memory stacks together in a single package.
The difficult part is the time each package spends moving through testing. Blackwell reportedly takes three to four times longer to test than Nvidia’s previous-generation Hopper, while Rubin could need as much as seven times longer than Hopper.
That has lengthened the queue for the machinery needed to expand output. Equipment lead times have reportedly moved from three to six months to as long as eight months.
TSMC has responded with unusual urgency. It reportedly placed this year’s equipment orders at existing prices, foregoing negotiations for discounts or extra features in order to secure capacity.
Cliff Hou, TSMC’s deputy co-COO, said that by July the company’s expected equipment needs had reached 1.9 times its original estimate as artificial intelligence demand accelerated. “Compared with the pattern 30 years ago, we have never seen the demand increase that much, that frequency of changes,” Hou said.
Against that backdrop, TSMC is weighing an increase of as much as 20% for CoWoS, according to Trendforce, which cited supply-chain sources and local media. The company has not confirmed that it will implement the increase, or when any change might take effect.
The potential repricing extends beyond packaging. TSMC is reportedly considering 2027 increases of 5% to 10% for wafers made on advanced process technologies. Customers using 2nm and 3nm-class nodes could face the largest rises, while customers seeking capacity above their original allocations may also face premiums that could lift some costs by as much as 25%.
TSMC is also seeking more room in the system. GlobalFoundries has agreed to make silicon interposers for TSMC’s CoWoS in the US under a five-year contract worth $2 billion, with production expected to ramp up in the first half of 2028.
Industry estimates cited by Trendforce put TSMC’s monthly capacity at over 106,000 wafers in 2026, with a target of 227,000 wafers in 2027.
The immediate issue is access as much as price. Buyers of advanced artificial intelligence chips need packaging capacity alongside the chips themselves, while rivals such as Intel face higher manufacturing costs and less flexibility if CoWoS allocations remain tight.
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